1. Field of the Invention
The present invention relates to a semiconductor device. More specifically, the present invention relates to a LOCOS offset field-effect transistor having a high breakdown voltage and a high current drivability.
2. Description of the Related Art
FIG. 2 illustrates an example of a conventional N-channel LOCOS offset MOS field-effect transistor having a high breakdown voltage structure. An N-channel LOCOS offset MOS field-effect transistor 101 includes a P-type silicon substrate 16, a P-type well region 17, a lightly-doped N-type source LOCOS offset region 18, a lightly-doped N-type drain LOCOS offset region 19, a heavily-doped N-type source region 20, a heavily-doped N-type drain region 21, a channel formation region 22, a gate oxide film 23, a gate electrode 24, LOCOS oxide films 25, a protective oxide film 26, a source electrode 27, a drain electrode 28, and the like. As illustrated in FIG. 2, features of the MOS field-effect transistor 101 reside in that the lightly-doped N-type drain LOCOS offset region 19 is formed between the channel formation region 22 and the heavily-doped N-type drain region 21 for the purpose of increasing a breakdown voltage, and in that the LOCOS oxide films 25 are each formed to be as thick as 5,000 Å to 10,000 Å for the purpose of preventing a channel formation in a parasitic field transistor formed between elements. In general a drain breakdown voltage of a MOS field-effect transistor having a large channel length is determined as a voltage at which an avalanche breakdown occurs in a portion to which the largest electric field is applied in a depletion layer formed at a boundary between the channel formation region and the drain region, that is, a surface portion which is the most sensitive to a gate potential. The reason for a high drain breakdown voltage of the MOS field-effect transistor 101 is that a bird's beak of the LOCOS oxide film 25 is positioned in the vicinity of the boundary surface between the channel formation region 22 and the offset region 19, alleviating the influence of the gate potential so that an avalanche breakdown may less likely occur.
Further reduction of a dopant concentration of the offset region 19 to increase a width of the depletion layer to obtain a higher breakdown voltage leads to an increase of the resistance of the offset region 19, causing a generation of Joule heat in the offset region 19 to break down the element at a turning on of the transistor to get a large drain current. There is a trade-off relationship between a high breakdown voltage and a current drivability.
In view of the above-mentioned problem, Japanese Patent Application Laid-open No. H 11-26766 proposes the following method. Japanese Patent Application Laid-open No. H11-26766 discloses a method of optimizing a film thickness of a LOCOS oxide film to a film thickness satisfying the following two conditions. The first condition is a film thickness condition as to whether to suppress the above-mentioned influence of the gate potential on the avalanche breakdown. The second condition is a film thickness condition as to whether or not the gate potential may allow the surface of the lightly-doped drain LOCOS offset region to enter an accumulated state. If the film thickness of the LOCOS oxide film is set to an optimum film thickness, a high breakdown voltage element having a high current drivability may be produced.
In a case where the above-mentioned conventional example is utilized to produce a high breakdown voltage element having a high current drivability, because the above-mentioned two conditions are inherently in a trade-off relationship, it is difficult to select an optimum film thickness satisfying the two conditions simultaneously.